1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuit products, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are formed on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (ON-state) and a high impedance state (OFF-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises a doped source region and a separate doped drain region that are formed in a semiconductor substrate. The source and drain regions are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure of the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. The gate structures for such FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. Trenches T are formed in the substrate B to define the fins C. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes to grow epitaxial semiconductor material in the source/drain regions. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction.
FETs, including FinFET transistor devices, have an isolation structure, e.g., a shallow trench isolation structure that is formed in the semiconducting substrate around the device so as to electrically isolate the transistor from adjacent transistors. Traditionally, isolation structures were always the first structures that were formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins. As FinFET devices have been scaled, i.e., reduced in size, to meet ever increasing performance and size requirements, the width W of the fins C has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm.
As the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches T in the substrate B to define multiple “fins” (i.e., a “sea of fins”) that extend across the substrate, and thereafter remove some of the fins C where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins C to very small dimensions due to the more uniform environment in which the etching process that forms the trenches T is performed.
FIGS. 1B-1I depict one illustrative prior art process, a so-called “Fins-cut-First” process, of forming fins and isolation structures on a product comprised of a plurality of FinFET devices. Accordingly, FIG. 1B depicts the device 10 after a patterned hard mask layer 14, e.g., a patterned layer of silicon nitride (pad nitride) along with a patterned layer of silicon dioxide (pad oxide), was formed above the substrate 12 in accordance with the desired fin pattern and pitch.
FIG. 1C depicts the device 10 after a fin-formation etching process was performed through the patterned masking layer 14 so as to define a plurality of trenches 17 in the substrate 12 that define the fins 15. The trenches 17 are formed to a depth 17D, which in some applications may be on the order of about 140-150 nm.
FIG. 1D depicts the device 10 after a layer of insulating material 18, such as flowable silicon dioxide (FCVD), was formed so as to overfill the trenches 17. The FCVD material may be selected so as to insure substantially complete filling of the relatively narrow and deep trenches 17, i.e., high aspect ratio trenches. One downside to the use of the FCVD material is that it is a relatively slow process that increases production time. A chemical mechanical polishing (CMP) process was then performed to planarize the upper surface of the insulating material 18 with the top of the patterned hard mask 14.
FIG. 1E depicts the device 10 after a patterned masking layer 20, e.g., a patterned layer of photoresist, was formed above the patterned hard mask layer 14 and the layer of insulating material 18. The patterned masking layer 20 has openings 20A, 20B that are positioned above the fins 15 to be removed to make room for the isolation structure. In this example, two fins will be removed to make room for the isolation structures. Of course, any number of fins may be removed. The opening 20A is depicted as being slightly misaligned.
FIG. 1F depicts the device 10 after an isolation-trench etching process was performed through the patterned masking layer 20 so as to define a plurality of trenches 22 in the substrate 12 that define the area where isolation structures will be formed. As depicted, the trenches 22 are deeper than the trenches 17. In one embodiment, the trenches 22 are formed to a depth 22D, which in some applications may be on the order of about 250 nm.
FIG. 1G depicts the product after several process operations were performed. First, another layer of insulating material 24, such as silicon dioxide formed by the well-known HARP process, was formed so as to overfill the trenches 22. The HARP process may be employed to fill the relatively wider trenches 22 because it is a faster process, thereby tending to increase production rates. After the deposition of the layer of insulating material 24, an anneal process may be performed to densify the various insulating materials. Then, a chemical mechanical polishing (CMP) process was performed to planarize the upper surface of the insulating material 24 with the top of the patterned hard mask 14.
FIG. 1H depicts the device 10 after the patterned hard mask layer 14 was removed (SiN strip followed by oxide deglaze).
FIG. 1I depicts the device 10 after an etch-back process was performed to recess the layers of insulating material 18, 24 between the fins 15 and thereby expose the upper portions of the fins 15, which corresponds to the final fin height of the fins 15. Unfortunately, due to the different etching characteristic of the insulating materials 18, 24, the recessed upper surface of the insulating materials 18, 24 is not level or uniform. Such a situation can result in several problems. For example, such an uneven surface may result in fins having an asymmetric profile, as indicated in the dashed-line region 26. That is, the height of the exposed sides of the fin may be significantly different, e.g., 6 nm or so. As a result of the asymmetric profile, epitaxial semiconductor material (not shown) formed in the source/drain regions on such asymmetric fins will not be uniform in nature, thereby creating additional downstream processing issues. Another problem that may arise using this prior art process is that some fins may only be partially removed, as depicted in the dashed-line region 28. Such a situation may occur to misalignment of the fin-cut mask 20. The presence of such partial fins may be problematic in that, depending upon the size and location of such partial fins, epi semiconductor material may undesirably form on such partial fins.
The present disclosure is directed to various methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices that may solve or reduce one or more of the problems identified above.